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| includes max 7000ae altera corporation 1 max 7000a programmable logic device september 2003, ver. 4.5 data sheet ds-m7000a-4.5 features... high-performance 3.3-v eeprom-based programmable logic devices (plds) built on second-generation multiple array matrix (max ? ) architecture (see table 1 ) 3.3-v in-system programmability (isp) through the built-in ieee std. 1149.1 joint test action group (jtag) interface with advanced pin-locking capability ? max 7000ae device in-system pr ogrammability (isp) circuitry compliant with ieee std. 1532 ? epm7128a and epm7256a device is p circuitry compatible with ieee std. 1532 built-in boundary-scan test (b st) circuitry compliant with ieee std. 1149.1 supports jedec jam standard te st and programming language (stapl) jesd-71 enhanced isp features ? enhanced isp algorithm for faster programming (excluding epm7128a and epm7256a devices) ? isp_done bit to ensure comple te programming (excluding epm7128a and epm7256a devices) ? pull-up resistor on i/o pins during in-system programming pin-compatible with the po pular 5.0-v max 7000s devices high-density plds ranging from 600 to 10,000 usable gates extended temperature range f for information on in-system prog rammable 5.0-v max 7000 or 2.5-v max 7000b devices, see the max 7000 programmable lo gic device family data sheet or the max 7000b programmable logic device family data sheet .
2 altera corporation max 7000a programmable logic device data sheet ...and more features 4.5-ns pin-to-pin logic delays with counter frequencies of up to 227.3 mhz multivolt tm i/o interface enables device core to run at 3.3 v, while i/o pins are compatible with 5.0- v, 3.3-v, and 2.5-v logic levels pin counts ranging from 44 to 256 in a variety of thin quad flat pack (tqfp), plastic quad flat pack (p qfp), ball-grid array (bga), space- saving fineline bga tm , and plastic j-lead chip carrier (plcc) packages supports hot-socketing in max 7000ae devices programmable interconnect array (p ia) continuous routing structure for fast, predictable performance pci-compatible bus-friendly architecture, including programmable slew-rate control open-drain output option programmable macrocell registers with individual clear, preset, clock, and clock enable controls programmable power-up states for macrocell registers in max 7000ae devices programmable power-saving mode for 50 % or greater power reduction in each macrocell configurable expander product-te rm distribution, allowing up to 32 product terms per macrocell programmable security bit for pr otection of proprietary designs 6 to 10 pin- or logic-driven output enable signals two global clock signals with optional inversion enhanced interconnect resources for improved routability fast input setup times provided by a dedicated path from i/o pin to macrocell registers programmable output slew-rate control programmable ground pins table 1. max 7000a device features feature epm7032ae epm7064ae epm7128ae epm7256ae epm7512ae usable gates 600 1,250 2,500 5,000 10,000 macrocells 32 64 128 256 512 logic array blocks 2 4 8 16 32 maximum user i/o pins 36 68 100 164 212 t pd (ns) 4.5 4.5 5.0 5.5 7.5 t su (ns) 2.9 2.8 3.3 3.9 5.6 t fsu (ns) 2.5 2.5 2.5 2.5 3.0 t co1 (ns) 3.0 3.1 3.4 3.5 4.7 f cnt (mhz) 227.3 222.2 192.3 172.4 116.3 altera corporation 3 max 7000a programmable logic device data sheet software design support and automat ic place-and-route provided by altera?s development systems for windows-based pcs and sun sparcstation, and hp 9000 series 700/800 workstations additional design entry and simulation support provided by edif 2 0 0 and 3 0 0 netlist files, librar y of parameterized modules (lpm), verilog hdl, vhdl, and other inte rfaces to popular eda tools from manufacturers such as cadence, exemplar logic, mentor graphics, orcad, synopsys, synplicity, and veribest programming support with altera ?s master programming unit (mpu), masterblaster tm serial/universal serial bus (usb) communications cable, byteblastermv tm parallel port download cable, and bitblaster tm serial download cable, as well as programming hardware from third-party manufacturers and any jam tm stapl file ( .jam ), jam byte-code file ( .jbc ), or serial vector format file- ( .svf ) capable in-circuit tester general description max 7000a (including max 7000ae) devices are high-density, high- performance devices based on altera?s second-generation max architecture. fabricated with adva nced cmos technology, the eeprom- based max 7000a devices operate with a 3.3-v supply voltage and provide 600 to 10,000 usable gates, isp, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 mh z. max 7000a devices in the -4, -5, -6, -7, and some -10 speed grades are compatible wi th the timing requirements for 33 mhz operation of the pci special interest group (pci sig) pci local bus specification, revision 2.2 . see table 2 . table 2. max 7000a speed grades device speed grade -4 -5 -6 -7 -10 -12 epm7032ae vvv epm7064ae vvv epm7128a vvvv epm7128ae vvv epm7256a vvvv epm7256ae vvv epm7512ae vvv 4 altera corporation max 7000a programmable logic device data sheet the max 7000a architecture supports 100 % transistor-to-transistor logic (ttl) emulation and high-density integration of ssi, msi, and lsi logic functions. it easily integrates multiple devices including pals, gals, and 22v10s devices. max 7000a devices ar e available in a wide range of packages, including plcc, bga, fineline bga, ultra fineline bga, pqfp, and tqfp packages. see table 3 and table 4 . notes to tables: (1) when the ieee std. 1149.1 (jtag) interface is used fo r in-system programming or bo undary-scan testing, four i/o pins become jtag pins. (2) all ultra fineline bga packages are footprint-compatible via the sameframe tm feature. therefore, designers can design a board to support a variety of devices, providing a flexible migration path across densities and pin counts. device migration is fully supported by altera development tools. see ?sameframe pin-outs? on page 15 for more details. (3) all fineline bga packages are footprint-compatible via the sameframe feature. therefore, designers can design a board to support a variety of devices, providing a flexib le migration path across densities and pin counts. device migration is fully supported by altera development tools. see ?sameframe pin-outs? on page 15 for more details. table 3. max 7000a maximum user i/o pins note (1) device 44-pin plcc 44-pin tqfp 49-pin ultra fineline bga (2) 84-pin plcc 100-pin tqfp 100-pin fineline bga (3) epm7032ae 36 36 epm7064ae 36 36 41 68 68 epm7128a 68 84 84 epm7128ae 68 84 84 epm7256a 84 epm7256ae 84 84 epm7512ae table 4. max 7000a maximum user i/o pins note (1) device 144-pin tqfp 169-pin ultra fineline bga (2) 208-pin pqfp 256-pin bga 256-pin fineline bga (3) epm7032ae epm7064ae epm7128a 100 100 epm7128ae 100 100 100 epm7256a 120 164 164 epm7256ae 120 164 164 epm7512ae 120 176 212 212 altera corporation 5 max 7000a programmable logic device data sheet max 7000a devices use cmos ee prom cells to implement logic functions. the user-con figurable max 7000a architecture accommodates a variety of independent combinatorial and sequential logic functions. the devices can be reprogrammed fo r quick and effici ent iterations during design development and debug cycles, and can be programmed and erased up to 100 times. max 7000a devices contain from 32 to 512 macrocells that are combined into groups of 16 macrocells, call ed logic array blocks (labs). each macrocell has a programmable- and /fixed- or array and a configurable register with independen tly programmable clock, clock enable, clear, and preset functions. to build complex logic functions, each macrocell can be supplemented with both shareable expander product terms and high- speed parallel expander product term s, providing up to 32 product terms per macrocell. max 7000a devices provide programm able speed/power optimization. speed-critical portions of a design can run at high speed/full power, while the remaining portions run at reduced speed/low power. this speed/power optimization feature enables the designer to configure one or more macrocells to operate at 50 % or lower power while adding only a nominal timing delay. max 7000a devi ces also provide an option that reduces the slew rate of the output buffers, minimizing noise transients when non-speed-critical signals are sw itching. the output drivers of all max 7000a devices can be set for 2.5 v or 3.3 v, and all input pins are 2.5-v, 3.3-v, and 5.0-v tolerant, al lowing max 7000a devices to be used in mixed-voltage systems. max 7000a devices are supported by altera development systems, which are integrated packages that offer schematic, text?including vhdl, verilog hdl, and the altera hardware description language (ahdl)?and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. the software provides edif 2 0 0 and 3 0 0, lp m, vhdl, verilog hdl, and other interfaces for additional design entry and simula tion support from other industry-standard pc- and unix-workstation-based eda tools. the software runs on windows-based pcs, as well as sun sparcstation, and hp 9000 series 700/800 workstations. f for more information on development tools, see the max+plus ii programmable logic development system & software data sheet and the quartus programmable logic development system & software data sheet . 6 altera corporation max 7000a programmable logic device data sheet functional description the max 7000a architecture incl udes the following elements: logic array blocks (labs) macrocells expander product terms (shareable and parallel) programmable inte rconnect array i/o control blocks the max 7000a architecture includes four dedicated inputs that can be used as general-purpose inputs or as high-speed, global control signals (clock, clear, and two output enable signals) for each macrocell and i/o pin. figure 1 shows the architecture of max 7000a devices. altera corporation 7 max 7000a programmable logic device data sheet figure 1. max 7000a device block diagram note: (1) epm7032ae, epm7064ae, epm7128a, epm7128ae, epm7256a, and epm7256ae devices have six output enables. epm7512ae devices have 10 output enables. logic array blocks the max 7000a device architecture is based on the linking of high-performance labs. labs consist of 16-macrocell arrays, as shown in figure 1 . multiple labs are linked together via the pia, a global bus that is fed by all dedicated input pins, i/o pins, and macrocells. each lab is fed by the following signals: 36 signals from the pi a that are used for general logic inputs global controls that are used for secondary register functions direct input paths from i/ o pins to the registers that are used for fast setup times 6 6 input/gclrn 6 or 10 output enables (1) 6 or 10 output enables (1) 16 36 36 16 i/o control block lab c lab d i/o control block 6 16 36 36 16 i/o control block lab a macrocells 1 to 16 lab b i/o control block 6 pia input/gclk1 input/oe2/gclk2 input/oe1 2 to 16 i/o 2 to 16 i/o 2 to 16 i/o 2 to 16 i/o 2 to 16 2 to 16 2 to 16 2 to 16 2 to 16 2 to 16 2 to 16 2 to 16 2 to 16 2 to 16 2 to 16 2 to 16 macrocells 17 to 32 macrocells 33 to 48 macrocells 49 to 64 8 altera corporation max 7000a programmable logic device data sheet macrocells max 7000a macrocells can be indivi dually configured for either sequential or combinatorial logic op eration. the macrocells consist of three functional blocks: the logic array, the prod uct-term select matrix, and the programmable register. figure 2 shows a max 7000a macrocell. figure 2. max 7000a macrocell combinatorial logic is implemented in the logic array, which provides five product terms per macrocell. the product-term select matrix allocates these product terms for use as eith er primary logic inputs (to the or and xor gates) to implement combinatorial functions, or as secondary inputs to the macrocell?s register preset, clock, and clock enable control functions. two kinds of expander product terms (?expanders?) are available to supplement macrocell logic resources: shareable expanders, which are inve rted product terms that are fed back into the logic array parallel expanders, which are prod uct terms borrowed from adjacent macrocells the altera development system auto matically optimizes product-term allocation according to the logi c requirements of the design. product- te r m select matrix 36 signals from pia 16 expander product terms lab local array parallel logic expanders (from other macrocells) shared logic expanders clear select global clear global clocks clock/ enable select 2 prn clrn d/t q ena register bypass to i/o control block from i/o pin to pia programmable register fast input select vcc altera corporation 9 max 7000a programmable logic device data sheet for registered functions, each macr ocell flipflop can be individually programmed to implement d, t, jk, or sr operation with programmable clock control. the flipflop can be by passed for combinatorial operation. during design entry, the designer sp ecifies the desired flipflop type; the altera software then selects the most efficient flipflop operation for each registered function to optimize resource utilization. each programmable register can be clocked in three different modes: global clock signal. th is mode achieves the fastest clock-to-output performance. global clock signal enabled by an active-high cloc k enable. a clock enable is generated by a product te rm. this mode provides an enable on each flipflop while still ac hieving the fast clock-to-output performance of the global clock. array clock implemented with a pr oduct term. in this mode, the flipflop can be clocked by signals fr om buried macroce lls or i/o pins. two global clock signals are availa ble in max 7000a devices. as shown in figure 1 , these global clock signals can be the true or the complement of either of the global clock pins, gclk1 or gclk2 . each register also supports asynchronous preset and clear functions. as shown in figure 2 , the product-term select ma trix allocates product terms to control these operations. although the product-term-driven preset and clear from the register are active high , active-low control can be obtained by inverting the signal within the logi c array. in addition, each register clear function can be individually driven by the active-low dedicated global clear pin ( gclrn ). upon power-up, each register in a max 7000ae device may be set to either a high or low state. this power-up state is specified at design entry. upon powe r-up, each register in epm7128a and epm7256a devices are set to a low state. all max 7000a i/o pins have a fast input path to a macrocell register. this dedicated path allows a signal to bypass the pia and combinatorial logic and be clocked to an input d flip flop with an extremely fast (as low as 2.5 ns) input setup time. 10 altera corporation max 7000a programmable logic device data sheet expander product terms although most logic func tions can be implemented with the five product terms available in each macrocell, more complex logic functions require additional produc t terms. another macrocell can be used to supply the required logic resources. however, the max 7000a architecture also offers both shareable and parallel expander product te rms that provide additional product terms directly to any macrocell in the same lab. these expanders help ensure that logic is synthesized with the fewest possible logic resources to obtain th e fastest possible speed. shareable expanders each lab has 16 shareable expanders that can be viewed as a pool of uncommitted single product terms (o ne from each macrocell) with inverted outputs that feed back in to the logic array. each shareable expander can be used and shared by any or all macrocells in the lab to build complex logic functions. a small delay ( t sexp ) is incurred when shareable expanders are used. figure 3 shows how shareable expanders can feed multiple macrocells. figure 3. max 7000a shareable expanders shareable expanders can be shared by any or all macro cells in an lab. macrocell product-term logic product-term select matrix macrocell product-term logic 36 signals from pia 16 shared expanders altera corporation 11 max 7000a programmable logic device data sheet parallel expanders parallel expanders are unused product terms that can be allocated to a neighboring macrocell to implement fast, complex logic functions. parallel expanders allow up to 20 pr oduct terms to directly feed the macrocell or logic, with five product term s provided by the macrocell and 15 parallel expanders provided by neig hboring macrocells in the lab. the compiler can allocate up to three sets of up to five parallel expanders to the macrocells that require addition al product terms. each set of five parallel expanders incurs a small, incremental timing delay ( t pexp ). for example, if a macrocell requires 14 pr oduct terms, the compiler uses the five dedicated product terms within the macrocell and allocates two sets of parallel expanders; the first set includes five prod uct terms, and the second set includes four product terms, increasing the total delay by 2 t pexp . two groups of eight macrocells within each lab (e.g., macrocells 1 through 8 and 9 through 16) form tw o chains to lend or borrow parallel expanders. a macrocell borrows parallel expanders from lower- numbered macrocells. for example, macrocell 8 can borrow parallel expanders from macrocell 7, from macr ocells 7 and 6, or from macrocells 7, 6, and 5. within each group of eight, the lowest-numbered macrocell can only lend parallel expanders, and the highest-numbered macrocell can only borrow them. figure 4 shows how parallel expanders can be borrowed from a neighboring macrocell. 12 altera corporation max 7000a programmable logic device data sheet figure 4. max 7000a parallel expanders unused product terms in a macrocell can be allocated to a neighboring macrocell. programmable inte rconnect array logic is routed between labs on the pia. this global bus is a programmable path that connects any signal source to any destination on the device. all max 7000a dedicated inputs, i/o pins, and macrocell outputs feed the pia, which makes th e signals availabl e throughout the entire device. only the signals requir ed by each lab are actually routed from the pia into the lab. figure 5 shows how the pia signals are routed into the lab. an eeprom cell co ntrols one input to a 2-input and gate, which selects a pia signal to drive into the lab. preset clock clear product- te r m select matrix preset clock clear product- te r m select matrix macrocell product- term logic from previous macrocell to next macrocell macrocell product- term logic 36 signals from pia 16 shared expanders altera corporation 13 max 7000a programmable logic device data sheet figure 5. max 7000a pia routing while the routing delays of channel -based routing schemes in masked or fpgas are cumulative, variable, and path-dependent, the max 7000a pia has a predictable delay. the pia makes a design?s timing performance easy to predict. i/o control blocks the i/o control block allows each i/o pin to be individually configured for input, output, or bidirectional operation. all i/o pins have a tri-state buffer that is individually controlled by one of the global output enable signals or directly connected to ground or v cc . figure 6 shows the i/o control block for max 7000a devices. the i/o control block has 6 or 10 global output enable signals that ar e driven by the true or complement of two output enable sign als, a subset of the i/o pins, or a subset of the i/o macrocells. to lab pia signals 14 altera corporation max 7000a programmable logic device data sheet figure 6. i/o control block of max 7000a devices when the tri-state buffer control is connected to ground, the output is tri-stated (high impedance) and the i/o pin can be used as a dedicated input. when the tri-state buffer control is connected to v cc , the output is enabled. the max 7000a architecture provid es dual i/o feedback, in which macrocell and pin feedbacks are in dependent. when an i/o pin is configured as an input, the associat ed macrocell can be used for buried logic. from macrocell fast input to macrocell register slew-rate control to pia to other i/o pins 6 or 10 global output enable signals (1) pia vcc open-drain output oe select multiplexer gnd note: (1) epm7032ae, epm7064ae, epm7128a, epm7128ae, epm725 6a, and epm7256ae devices have six output enable signals. epm7512ae devices have 10 output enable signals. altera corporation 15 max 7000a programmable logic device data sheet sameframe pin-outs max 7000a devices support the sameframe pin-out feature for fineline bga packages. the same frame pin-out feature is the arrangement of balls on fineline bga packages such that the lower-ball- count packages form a subset of the higher-ball-count packages. sameframe pin-outs provide the flex ibility to migrate not only from device to device within the same pack age, but also from one package to another. a given printed circuit board (pcb) layout can support multiple device density/package combinations. for example, a single board layout can support a range of devices from an epm7128ae device in a 100-pin fineline bga package to an ep m7512ae device in a 256-pin fineline bga package. the altera design software provid es support to design pcbs with sameframe pin-out devices. devices ca n be defined for present and future use. the software generates pin-outs describing how to lay out a board to take advantage of this migration (see figure 7 ). figure 7. sameframe pin-out example designed for 256-pin fineline bga package printed circuit board 100-pin fineline bga package (reduced i/o count or logic requirements) 256-pin fineline bga package (increased i/o count or logic requirements) 100-pin fineline bga 256-pin fineline bga 16 altera corporation max 7000a programmable logic device data sheet in-system programma- bility max 7000a devices can be programm ed in-system via an industry- standard 4-pin ieee std. 1149.1 (jtag) in terface. isp offers quick, efficient iterations during design develo pment and debugging cycles. the max 7000a architecture internally generates the high programming voltages required to program eeprom cells, allowing in-system programming with only a single 3. 3-v power supply. during in-system programming, the i/o pins are tr i-stated and weakly pulled-up to eliminate board conflicts. the pull-up value is nominally 50 k ? . max 7000ae devices have an enhanced isp algorithm for faster programming. these devices also offer an isp_done bit that provides safe operation when in-system programming is interrupted. this isp_done bit, which is the last bit programmed , prevents all i/o pins from driving until the bit is programm ed. this feature is only available in epm7032ae, epm7064ae, epm7128ae, epm 7256ae, and epm7512ae devices. isp simplifies the manufacturing flow by allowing devices to be mounted on a pcb with standard pick-and-p lace equipment before they are programmed. max 7000a devices can be programmed by downloading the information via in-circuit tester s, embedded processors, the altera masterblaster serial/usb communicatio ns cable, byteblastermv parallel port download cable, and bitblaster serial download cable. programming the devices after they are placed on the board eliminates lead damage on high-pin-count packages (e.g., qfp packages) due to device handling. max 7000a devices can be reprogramm ed after a system has already shipped to the field. for example, pr oduct upgrades can be performed in the field via software or modem. in-system programming can be accompli shed with either an adaptive or constant algorithm. an adaptive al gorithm reads information from the unit and adapts subsequent progra mming steps to achieve the fastest possible programming time for that un it. a constant algorithm uses a pre- defined (non-adaptive) programming sequence that does not take advantage of adaptive algorithm programming time improvements. some in-circuit testers cannot prog ram using an adaptive algorithm. therefore, a constant algorithm mus t be used. max 7000ae devices can be programmed with eith er an adaptive or constant (non-adaptive) algorithm. epm7128a and epm7256a device can only be programmed with an adaptive algo rithm; users programming these two devices on platforms that cannot use an adapti ve algorithm shou ld use epm7128ae and epm7256ae devices. the jam standard test and progra mming language (stapl), jedec standard jesd 71, can be used to program max 7000a devices with in- circuit testers, pcs, or embedded processors. altera corporation 17 max 7000a programmable logic device data sheet f for more information on usin g the jam stapl language, see application note 88 (using the jam language for isp & icr via an embedded processor) and application note 122 (usi ng jam stapl for isp & icr via an embedded processor) . isp circuitry in max 7000a e devices is compliant with the ieee std. 1532 specification. the ieee std. 1532 is a standard developed to allow concurrent isp between multiple pld vendors. programming sequence during in-system programming, instructions, addresses, and data are shifted into the max 7000a device through the tdi input pin. data is shifted out through the tdo output pin and compared against the expected data. programming a pattern into the device requires the following six isp stages. a stand-alone verification of a programmed pattern involves only stages 1, 2, 5, and 6. 1. enter isp . the enter isp stage ensures th at the i/o pins transition smoothly from user mode to isp mode. the enter isp stage requires 1ms. 2. check id . before any program or verify process, the silicon id is checked. the time required to read this silicon id is relatively small compared to the overall programming time. 3. bulk erase . erasing the device in-system involves shifting in the instructions to erase the device and applying one erase pulse of 100 ms. 4. program . programming the device in-sys tem involves shifting in the address and data and then applying the programming pulse to program the eeprom cells. this process is repeated for each eeprom address. 5. verify . verifying an altera device in-system involves shifting in addresses, applying the read puls e to verify the eeprom cells, and shifting out the data for comparis on. this process is repeated for each eeprom address. 6. exit isp . an exit isp stage ensures that the i/o pins transition smoothly from isp mode to user mode. the exit isp stage requires 1ms. 18 altera corporation max 7000a programmable logic device data sheet programming times the time required to implement each of the six programming stages can be broken into the fo llowing two elements: a pulse time to erase, progra m, or read the eeprom cells. a shifting time based on the test clock ( tck ) frequency and the number of tck cycles to shift instructions , address, and data into the device. by combining the pulse and shift ti mes for each of the programming stages, the program or verify time ca n be derived as a function of the tck frequency, the number of devices, and specific target device(s). because different isp-capable devices have a different number of eeprom cells, both the total fixed and total variable times are unique for a single device. programming a single max 7000a device the time required to program a si ngle max 7000a device in-system can be calculated from the following formula: where: t prog = programming time t ppulse = sum of the fixed times to erase, program, and verify the eeprom cells cycle ptck =number of tck cycles to program a device f tck = tck frequency the isp times for a stand-alone verifica tion of a single max 7000a device can be calculated from the following formula: where: t ver =verify time t vpulse = sum of the fixed times to verify the eeprom cells cycle vtck =number of tck cycles to verify a device t prog t ppulse cycle ptck f tck ------------------------------- - + = t ver t vpulse cycle vtck f tck -------------------------------- + = altera corporation 19 max 7000a programmable logic device data sheet the programming times described in tables 5 through 7 are associated with the worst-case method using the enhanced isp algorithm. tables 6 and 7 show the in-system programming and stand alone verification times for several common test clock frequencies. table 5. max 7000a t pulse & cycle tck values device programming stand-alone verification t ppulse (s) cycle ptck t vpulse (s) cycle vtck epm7032ae 2.00 55,000 0.002 18,000 epm7064ae 2.00 105,000 0.002 35,000 epm7128ae 2.00 205,000 0.002 68,000 epm7256ae 2.00 447,000 0.002 149,000 epm7512ae 2.00 890,000 0.002 297,000 epm7128a (1) 5.11 832,000 0.03 528,000 epm7256a (1) 6.43 1,603,000 0.03 1,024,000 table 6. max 7000a in-system pr ogramming times for differ ent test clock frequencies device f tck units 10 mhz 5 mhz 2 mhz 1 mhz 500 khz 200 khz 100 khz 50 khz epm7032ae 2.01 2.01 2.03 2.06 2.11 2.28 2.55 3.10 s epm7064ae 2.01 2.02 2.05 2.11 2.21 2.53 3.05 4.10 s epm7128ae 2.02 2.04 2.10 2.21 2.41 3.03 4.05 6.10 s epm7256ae 2.05 2.09 2.23 2.45 2.90 4.24 6.47 10.94 s epm7512ae 2.09 2.18 2.45 2.89 3.78 6.45 10.90 19.80 s epm7128a (1) 5.19 5.27 5.52 5.94 6.77 9.27 13.43 21.75 s epm7256a (1) 6.59 6.75 7.23 8.03 9.64 14.45 22.46 38.49 s 20 altera corporation max 7000a programmable logic device data sheet note to tables: (1) epm7128a and epm7256a devices can only be programme d with an adaptive algorithm ; users programming these two devices on platforms that cannot use an adaptive algorithm should use epm7128ae and epm7256ae devices. programming with external hardware max 7000a devices can be programmed on windows-based pcs with an altera logic programmer card, the mpu, and the appropriate device adapter. the mpu performs contin uity checks to ensure adequate electrical contact between the adapter and the device. f for more information, see the altera programming hardware data sheet . the altera software can use text- or waveform-format test vectors created with the altera text editor or wav eform editor to test the programmed device. for added design verification , designers can perform functional testing to compare the functional devi ce behavior with the results of simulation. data i/o, bp microsystems, an d other programming hardware manufacturers provide programmin g support for altera devices. f for more information, see programming hard ware manufacturers . ieee std. 1149.1 (jtag) boundary-scan support max 7000a devices include the jtag bst circuitry defined by ieee std. 1149.1. table 8 describes the jtag instruct ions supported by max 7000a devices. the pin-out tables, available from the altera web site ( http://www.altera.com ), show the location of the jtag control pins for each device. if the jtag interface is not required, the jtag pins are available as user i/o pins. table 7. max 7000a stand-alone verification ti mes for different test clock frequencies device f tck units 10 mhz 5 mhz 2 mhz 1 mhz 500 khz 200 khz 100 khz 50 khz epm7032ae 0.00 0.01 0.01 0.02 0.04 0.09 0.18 0.36 s epm7064ae 0.01 0.01 0.02 0.04 0.07 0.18 0.35 0.70 s epm7128ae 0.01 0.02 0.04 0.07 0.14 0.34 0.68 1.36 s epm7256ae 0.02 0.03 0.08 0.15 0.30 0.75 1.49 2.98 s epm7512ae 0.03 0.06 0.15 0.30 0.60 1.49 2.97 5.94 s epm7128a (1) 0.08 0.14 0.29 0.56 1.09 2.67 5.31 10.59 s epm7256a (1) 0.13 0.24 0.54 1.06 2.08 5.15 10.27 20.51 s altera corporation 21 max 7000a programmable logic device data sheet table 8. max 7000a jtag instructions jtag instruction description sample/preload allows a snapshot of signals at t he device pins to be c aptured and examined during normal device operation, and permits an initia l data pattern output at the device pins extest allows the external circui try and board-level inte rconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins bypass places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through a select ed device to adjacent devices during normal device operation idcode selects the idcode regist er and places it between the tdi and tdo pins, allowing the idcode to be serially shifted out of tdo usercode selects the 32-bit usercode register and places it between the tdi and tdo pins, allowing the usercode value to be shifted out of tdo . the usercode instruction is available for max 7000ae devices only uescode these instructions select the user electronic signature (u escode) and allow the uescode to be shifted out of tdo . uescode instructions are available for epm7128a and epm7256a devices only. isp instructions these instructions are used when programming max 7000a devic es via the jtag ports with the masterblaster, byteblastermv, or bitblaster download cable, or using a jam stapl file, jbc file, or svf file vi a an embedded processor or test equipment. 22 altera corporation max 7000a programmable logic device data sheet the instruction register length of ma x 7000a devices is 10 bits. the user electronic signature (ues) register le ngth in max 7000a de vices is 16 bits. the max 7000ae usercode regi ster length is 32 bits. tables 9 and 10 show the boundary-scan register length and device idcode information for max 7000a devices. notes: (1) the most significant bit (msb) is on the left. (2) the least significant bit (lsb) for all jtag idcodes is 1 . f see application note 39 (ieee 1149.1 (jtag) boundary-scan testing in altera devices) for more information on jtag bst. table 9. max 7000a boundary-scan register length device boundary-scan register length epm7032ae 96 epm7064ae 192 epm7128a 288 epm7128ae 288 epm7256a 480 epm7256ae 480 epm7512ae 624 table 10. 32-bit max 7000a device idcode note (1) device idcode (32 bits) version (4 bits) part number (16 bits) manufacturer?s identity (11 bits) 1 (1 bit) (2) epm7032ae 0001 0111 0000 0011 0010 00001101110 1 epm7064ae 0001 0111 0000 0110 0100 00001101110 1 epm7128a 0000 0111 0001 0010 1000 00001101110 1 epm7128ae 0001 0111 0001 0010 1000 00001101110 1 epm7256a 0000 0111 0010 0101 0110 00001101110 1 epm7256ae 0001 0111 0010 0101 0110 00001101110 1 epm7512ae 0001 0111 0101 0001 0010 00001101110 1 altera corporation 23 max 7000a programmable logic device data sheet figure 8 shows timing information for the jtag signals. figure 8. max 7000a jtag waveforms table 11 shows the jtag timing parameters and values for max 7000a devices. note: (1) timing parameters shown in this tabl e apply for all specified vccio levels. table 11. jtag timing parameters & values for max 7000a devices note (1) symbol parameter min max unit t jcp tck clock period 100 ns t jch tck clock high time 50 ns t jcl tck clock low time 50 ns t jpsu jtag port setup time 20 ns t jph jtag port hold time 45 ns t jpco jtag port clock to output 25 ns t jpzx jtag port high impedance to valid output 25 ns t jpxz jtag port valid output to high impedance 25 ns t jssu capture register setup time 20 ns t jsh capture register hold time 45 ns t jsco update register clock to output 25 ns t jszx update register high impedance to valid output 25 ns t jsxz update register valid output to high impedance 25 ns tdo tck t jpzx t jpco t jph t jpxz t jcp t jpsu t jcl t jch tdi tms signal to be captured signal to be driven t jszx t jssu t jsh t jsco t jsxz 24 altera corporation max 7000a programmable logic device data sheet programmable speed/power control max 7000a devices offer a power-saving mode that supports low-power operation across user-defined signal paths or the entire device. this feature allows total power dissipation to be reduced by 50 % or more because most logic applications require only a small fraction of all gates to operate at maximum frequency. the designer can program each in dividual macrocell in a max 7000a device for either high-speed (i.e., with the turbo bit tm option turned on) or low-power operation (i.e., with th e turbo bit option turned off). as a result, speed-critical paths in the desi gn can run at high speed, while the remaining paths can operate at reduced power. macrocells that run at low power incur a nominal timing delay adder ( t lpa ) for the t lad , t lac , t ic , t en , t sexp , t acl , and t cppw parameters. output configuration max 7000a device outputs can be programmed to meet a variety of system-level requirements. multivolt i/o interface the max 7000a device architecture su pports the multivolt i/o interface feature, which allows max 7000a devices to connect to systems with differing supply voltages. max 7000a de vices in all packages can be set for 2.5-v, 3.3-v, or 5.0-v i/o pin oper ation. these devices have one set of vcc pins for internal operation and input buffers ( vccint ), and another set for i/o output drivers ( vccio ). the vccio pins can be connected to either a 3.3-v or 2.5-v power supply, depending on the output requirements. when the vccio pins are connected to a 2.5-v power supply, the output levels are compatible with 2.5-v systems. when the vccio pins are connected to a 3.3-v power supply, the output high is at 3.3 v an d is therefore compatible with 3.3-v or 5.0-v systems. devices operating with v ccio levels lower than 3.0 v incur a slightly greater timing delay of t od2 instead of t od1 . inputs can always be driven by 2.5-v, 3.3-v, or 5.0-v signals. table 12 describes the max 7000a multivolt i/o support. table 12. max 7000a multivolt i/o support v ccio voltage input signal (v) output signal (v) 2.5 3.3 5.0 2.5 3.3 5.0 2.5 vvvv 3.3 vvv vv altera corporation 25 max 7000a programmable logic device data sheet open-drain output option max 7000a devices provide an optional open-drain (equivalent to open-collector) output for each i/o pi n. this open-drain output enables the device to provide system-level control signals (e.g., interrupt and write enable signals) that can be asse rted by any of several devices. this output can also provid e an additional wired- or plane. open-drain output pins on max 7000a devices (with a pull-up resistor to the 5.0-v supply) can drive 5.0-v cmos input pins that require a high v ih . when the open-drain pin is active, it will drive low. when the pin is inactive, the resistor will pull up the trace to 5.0 v to meet cmos v oh requirements. the open-drain pin will only drive low or tri-state; it will never drive high. the rise time is de pendent on the valu e of the pull-up resistor and load impedance. the i ol current specification should be considered when selecting a pull-up resistor. programmable ground pins each unused i/o pin on max 7000a devices may be used as an additional ground pin. in epm7128a and epm7256a devices, utilizing unused i/o pins as additi onal ground pins requir es using the associated macrocell. in max 7000ae devices, this programmable ground feature does not require the use of the associat ed macrocell; therefore, the buried macrocell is still available for user logic. slew-rate control the output buffer for each max 7000a i/o pin has an adjustable output slew rate that can be configured for low-noise or high-speed performance. a faster slew rate provides high-sp eed transitions for high-performance systems. however, these fast transi tions may introduce noise transients into the system. a slow slew rate reduces system noise, but adds a nominal delay of 4 to 5 ns. when the co nfiguration cell is turned off, the slew rate is set for low-noise performance. each i/o pin has an individual eeprom bit that controls the slew rate, allowing designers to specify the slew rate on a pin-by-pin basis. the sl ew rate control affe cts both the rising and falling edges of the output signal. 26 altera corporation max 7000a programmable logic device data sheet power sequencing & hot-socketing because max 7000a devices can be used in a mixed-voltage environment, they have been designed specifically to tolerate any possible power-up sequence. the v ccio and v ccint power planes can be powered in any order. signals can be driven into max 7000a e devices before and during power- up (and power-down) without dama ging the device . additionally, max 7000ae devices do not drive out during power-up. once operating conditions are reached, max 7000ae de vices operate as specified by the user. max 7000ae device i/o pins will not source or sink more than 300 a of dc current during power-up. all pins can be driven up to 5.75 v during hot-socketing, except the oe1 and glcrn pins. the oe1 and glcrn pins can be driven up to 3.6 v during hot-socketing. after v ccint and v ccio reach the recommended operating cond itions, these two pins are 5.0-v tolerant. epm7128a and epm7256a devices do not support hot-socketing and may drive out during power-up. design security all max 7000a devices contain a progra mmable security bit that controls access to the data programmed in to the device. when this bit is programmed, a design implemented in the device cannot be copied or retrieved. this feature provides a hi gh level of design security because programmed data within eeprom cells is invisible. the se curity bit that controls this function, as well as a ll other programmed data, is reset only when the device is reprogrammed. generic testing max 7000a devices are fully tested . complete testing of each programmable eeprom bit and all in ternal logic elements ensures 100 % programming yield. ac test measurements are taken under conditions equivalent to those shown in figure 9 . test patterns can be used and then erased during early stages of the production flow. altera corporation 27 max 7000a programmable logic device data sheet figure 9. max 7000a ac test conditions operating conditions tables 13 through 16 provide information on absolute maximum ratings, recommended operating conditions, operating conditions, and capacitance for max 7000a devices. v cc to test system c1 (includes jig capacitance) device input rise and fall times < 2 ns device output 703 ? [521 ? ] 586 ? [481 ? ] power supply transients can affect ac measurements. simult aneous transitions of multiple outputs should be avoided for accurate measurement. threshold tests must not be performed under ac conditions. large-ampl itude, fast-ground- current transients no rmally occur as the device outputs discharge the load capacitances. when th ese transients flow through the parasitic inductance between the device ground pin and the test system ground, significant reductions in observable noise immunity can result. numbers in brackets are for 2.5-v outputs. numbers with out brackets are for 3.3-v outputs. table 13. max 7000a device absolute maximum ratings note (1) symbol parameter conditions min max unit v cc supply voltage with respect to ground (2) ?.5 4.6 v v i dc input voltage ?.0 5.75 v i out dc output current, per pin ?5 25 ma t stg storage temperature no bias ?5 150 c t a ambient temperature under bias ?5 135 c t j junction temperature bga, fineline bga, pqfp, and tqfp packages, under bias 135 c 28 altera corporation max 7000a programmable logic device data sheet table 14. max 7000a device recommended operating conditions symbol parameter conditions min max unit v ccint supply voltage for internal logic and input buffers (3) , (13) 3.0 3.6 v v ccio supply voltage for output drivers, 3.3-v operation (3) 3.0 3.6 v supply voltage for output drivers, 2.5-v operation (3) 2.3 2.7 v v ccisp supply voltage during in- system programming 3.0 3.6 v v i input voltage (4) ?.5 5.75 v v o output voltage 0 v ccio v t a ambient temperature commercial range 0 70 c industrial range (5) ?0 85 c t j junction temperature commercial range 0 90 c industrial range (5) ?0 105 ?c extended range (5) ?0 130 ?c t r input rise time 40 ns t f input fall time 40 ns altera corporation 29 max 7000a programmable logic device data sheet table 15. max 7000a device dc operating conditions note (6) symbol parameter conditions min max unit v ih high-level input voltage 1.7 5.75 v v il low-level input voltage ?.5 0.8 v v oh 3.3-v high-level ttl output voltage i oh = ? ma dc, v ccio = 3.00 v (7) 2.4 v 3.3-v high-level cmos output voltage i oh = ?.1 ma dc, v ccio = 3.00 v (7) v ccio ?0.2 v 2.5-v high-level output voltage i oh = ?00 a dc, v ccio = 2.30 v (7) 2.1 v i oh = ? ma dc, v ccio = 2.30 v (7) 2.0 v i oh = ? ma dc, v ccio = 2.30 v (7) 1.7 v v ol 3.3-v low-level ttl output voltage i ol = 8 ma dc, v ccio = 3.00 v (8) 0.45 v 3.3-v low-level cmos output voltage i ol = 0.1 ma dc, v ccio = 3.00 v (8) 0.2 v 2.5-v low-level output voltage i ol = 100 a dc, v ccio = 2.30 v (8) 0.2 v i ol = 1 ma dc, v ccio = 2.30 v (8) 0.4 v i ol = 2 ma dc, v ccio = 2.30 v (8) 0.7 v i i input leakage current v i = ?.5 to 5.5 v (9) ?0 10 a i oz tri-state output off-state current v i = ?.5 to 5.5 v (9) ?0 10 a r isp value of i/o pin pull-up resistor during in-system programming or during power-up v ccio = 3.0 to 3.6 v (10) 20 50 k ? v ccio = 2.3 to 2.7 v (10) 30 80 k ? v ccio = 2.3 to 3.6 v (11) 20 74 k ? table 16. max 7000a device capacitance note (12) symbol parameter conditions min max unit c in input pin capacitance v in = 0 v, f = 1.0 mhz 8 pf c i/o i/o pin capacitance v out = 0 v, f = 1.0 mhz 8 pf 30 altera corporation max 7000a programmable logic device data sheet notes to tables: (1) see the operating requirements for altera devices data sheet. (2) minimum dc input voltage is ?0.5 v. during transitions, the inputs may unde rshoot to ?2.0 v for input currents less than 100 ma and periods shorter than 20 ns. (3) for epm7128a and epm7256a devices only, v cc must rise monotonically. (4) in max 7000ae devices, all pins, including dedicated inputs, i/o pins, and jtag pins, may be driven before v ccint and v ccio are powered. (5) these devices support in-system programming for ?40 to 100 c. for in-system programming support between ?40 and 0 c, contact altera applications. (6) these values are specified under the re commended operating co nditions shown in table 14 on page 28 . (7) the parameter is measured with 50 % of the outputs each sourcing the specified current. the i oh parameter refers to high-level ttl or cmos output current. (8) the parameter is measured with 50 % of the outputs each sinking the specified current. the i ol parameter refers to low-level ttl or cmos output current. (9) this value is specified for normal device operation. for max 7000ae devices, the maximum leakage current during power-up is 300 a. for epm7128a and epm7256a devices, leakag e current during power-up is not specified. (10) for epm7128a and epm7256a devices, this pull-up exists while a device is programmed in-system. (11) for max 7000ae devices, this pull-up exists while devices are programmed in-system and in unprogrammed devices during power-up. (12) capacitance is measured at 25 c and is sample-tested only. the oe1 pin (high-voltage pin during programming) has a maximum capacitance of 20 pf. (13) the por time for max 7000ae devices (except max 7128a and max 7256a devices) does not exceed 100 s. the sufficient v ccint voltage level for por is 3.0 v. the device is fully initialized within the por time after v ccint reaches the sufficient por voltage level. altera corporation 31 max 7000a programmable logic device data sheet figure 10 shows the typical output driv e characteristics of max 7000a devices. figure 10. output drive charac teristics of max 7000a devices timing model max 7000a device timing can be anal yzed with the altera software, a variety of popular industry-stand ard eda simulators and timing analyzers, or with the timing model shown in figure 11 . max 7000a devices have predictable internal de lays that enable the designer to determine the worst-case timing of any design. the software provides timing simulation, point-to-point delay prediction, and detailed timing analysis for device-wide performance evaluation. v o output voltage (v) 1234 0 0 50 i ol i oh v ccint = 3.3 = 25 c v v cci o = 3.3 v temperature 100 150 typical i output current (ma) o v o output voltage (v) 1234 v ccint = 3.3 v v cci o = 2.5 v i oh 2.5 v 3.3 v typical i output current (ma) o v o output voltage (v) 1234 5 i oh v ccint = 3.3 v v cci o = 3.3 v typical i output current (ma) o v o output voltage (v) 1234 v ccint = 3.3 v v cci o = 2.5 v i oh t 2.5 v 3.3 v typical i output current (ma) o epm7128a & epm7256a devices epm7128a & epm7256a devices 0 0 50 i ol 100 150 0 0 40 i ol 80 120 0 40 i ol 80 120 o = 25 c temperature o 5 max 7000ae devices max 7000ae devices 5 5 = 25 c emperature o t = 25 c emperature o 32 altera corporation max 7000a programmable logic device data sheet figure 11. max 7000a timing model the timing characteristic s of any signal path can be derived from the timing model and parameters of a pa rticular device. external timing parameters, which represen t pin-to-pin timing dela ys, can be calculated as the sum of internal parameters. figure 12 shows the timing relationship between internal and external delay parameters. f see application note 94 (understanding max 7000 timing) for more information. logic array delay t lad output delay t od3 t od2 t od1 t xz z t x1 t zx2 t zx3 input delay t in register delay t su t h t pre t clr t rd t comb t fsu t fh pia delay t pia shared expander delay t sexp register control delay t lac t ic t en i/o delay t io global control delay t glob internal output enable delay t ioe parallel expander delay t pexp fast input delay t fin altera corporation 33 max 7000a programmable logic device data sheet figure 12. max 7000a switching waveforms combinatorial mode input pin i/o pin pia delay shared expander delay logic array input parallel expander delay logic array output output pin t in t lac , t lad t pia t od t pexp t io t sexp t comb global clock mode global clock pin global clock at register data or enable (logic array output) t f t ch t cl t r t in t glob t su t h array clock mode input or i/o pin clock into pia clock into logic array clock at register data from logic array register to pia to logic array register output to pin t f t r t ach t acl t su t in t io t rd t pia t clr , t pre t h t pia t ic t pia t od t od t r & t f < 2 ns. inputs are driven at 3 v for a logic high and 0 v for a logic low. all timing characteristics are measured at 1.5 v. 34 altera corporation max 7000a programmable logic device data sheet tables 17 through 30 show epm7032ae, epm7064ae, epm7128ae, epm7256ae, epm7512ae, epm 7128a, and epm7256a timing information. table 17. epm7032ae external timing parameters note (1) symbol parameter conditions speed grade unit -4 -7 -10 min max min max min max t pd1 input to non-registered output c1 = 35 pf (2) 4.5 7.5 10 ns t pd2 i/o input to non-registered output c1 = 35 pf (2) 4.5 7.5 10 ns t su global clock setup time (2) 2.9 4.7 6.3 ns t h global clock hold time (2) 0.0 0.0 0.0 ns t fsu global clock setup time of fast input 2.5 3.0 3.0 ns t fh global clock hold time of fast input 0.0 0.0 0.0 ns t co1 global clock to output delay c1 = 35 pf 1.0 3.0 1.0 5.0 1.0 6.7 ns t ch global clock high time 2.0 3.0 4.0 ns t cl global clock low time 2.0 3.0 4.0 ns t asu array clock setup time (2) 1.6 2.5 3.6 ns t ah array clock hold time (2) 0.3 0.5 0.5 ns t aco1 array clock to output delay c1 = 35 pf (2) 1.04.31.07.21.09.4 ns t ach array clock high time 2.0 3.0 4.0 ns t acl array clock low time 2.0 3.0 4.0 ns t cppw minimum pulse width for clear and preset (3) 2.0 3.0 4.0 ns t cnt minimum global clock period (2) 4.4 7.2 9.7 ns f cnt maximum internal global clock frequency (2) , (4) 227.3 138.9 103.1 mhz t acnt minimum array clock period (2) 4.4 7.2 9.7 ns f acnt maximum internal array clock frequency (2) , (4) 227.3 138.9 103.1 mhz altera corporation 35 max 7000a programmable logic device data sheet table 18. epm7032ae internal timing parameters (part 1 of 2) note (1) symbol parameter conditions speed grade unit -4 -7 -10 min max min max min max t in input pad and buffer delay 0.7 1.2 1.5 ns t io i/o input pad and buffer delay 0.7 1.2 1.5 ns t fin fast input delay 2.3 2.8 3.4 ns t sexp shared expander delay 1.9 3.1 4.0 ns t pexp parallel expander delay 0.5 0.8 1.0 ns t lad logic array delay 1.5 2.5 3.3 ns t lac logic control array delay 0.6 1.0 1.2 ns t ioe internal output enable delay 0.0 0.0 0.0 ns t od1 output buffer and pad delay, slow slew rate = off v ccio = 3.3 v c1 = 35 pf 0.8 1.3 1.8 ns t od2 output buffer and pad delay, slow slew rate = off v ccio = 2.5 v c1 = 35 pf (5) 1.3 1.8 2.3 ns t od3 output buffer and pad delay, slow slew rate = on v ccio = 2.5 v or 3.3 v c1 = 35 pf 5.8 6.3 6.8 ns t zx1 output buffer enable delay, slow slew rate = off v ccio = 3.3 v c1 = 35 pf 4.0 4.0 5.0 ns t zx2 output buffer enable delay, slow slew rate = off v ccio = 2.5 v c1 = 35 pf (5) 4.5 4.5 5.5 ns t zx3 output buffer enable delay, slow slew rate = on v ccio = 3.3 v c1 = 35 pf 9.0 9.0 10.0 ns t xz output buffer disable delay c1 = 5 pf 4.0 4.0 5.0 ns t su register setup time 1.3 2.0 2.8 ns t h register hold time 0.6 1.0 1.3 ns t fsu register setup time of fast input 1.0 1.5 1.5 ns t fh register hold time of fast input 1.5 1.5 1.5 ns t rd register delay 0.7 1.2 1.5 ns t comb combinatorial delay 0.6 1.0 1.3 ns 36 altera corporation max 7000a programmable logic device data sheet t ic array clock delay 1.2 2.0 2.5 ns t en register enable time 0.6 1.0 1.2 ns t glob global control delay 0.8 1.3 1.9 ns t pre register preset time 1.2 1.9 2.6 ns t clr register clear time 1.2 1.9 2.6 ns t pia pia delay (2) 0.9 1.5 2.1 ns t lpa low-power adder (6) 2.5 4.0 5.0 ns table 18. epm7032ae internal timing parameters (part 2 of 2) note (1) symbol parameter conditions speed grade unit -4 -7 -10 min max min max min max altera corporation 37 max 7000a programmable logic device data sheet table 19. epm7064ae external timing parameters note (1) symbol parameter conditions speed grade unit -4 -7 -10 min max min max min max t pd1 input to non- registered output c1 = 35 pf (2) 4.5 7.5 10.0 ns t pd2 i/o input to non- registered output c1 = 35 pf (2) 4.5 7.5 10.0 ns t su global clock setup time (2) 2.8 4.7 6.2 ns t h global clock hold time (2) 0.0 0.0 0.0 ns t fsu global clock setup time of fast input 2.5 3.0 3.0 ns t fh global clock hold time of fast input 0.0 0.0 0.0 ns t co1 global clock to output delay c1 = 35 pf 1.0 3.1 1.0 5.1 1.0 7.0 ns t ch global clock high time 2.0 3.0 4.0 ns t cl global clock low time 2.0 3.0 4.0 ns t asu array clock setup time (2) 1.6 2.6 3.6 ns t ah array clock hold time (2) 0.3 0.4 0.6 ns t aco1 array clock to output delay c1 = 35 pf (2) 1.0 4.3 1.0 7.2 1.0 9.6 ns t ach array clock high time 2.0 3.0 4.0 ns t acl array clock low time 2.0 3.0 4.0 ns t cppw minimum pulse width for clear and preset (3) 2.0 3.0 4.0 ns t cnt minimum global clock period (2) 4.5 7.4 10.0 ns f cnt maximum internal global clock frequency (2) , (4) 222.2 135.1 100.0 mhz t acnt minimum array clock period (2) 4.5 7.4 10.0 ns f acnt maximum internal array clock frequency (2) , (4) 222.2 135.1 100.0 mhz 38 altera corporation max 7000a programmable logic device data sheet table 20. epm7064ae internal timing parameters (part 1 of 2) note (1) symbol parameter conditions speed grade unit -4 -7 -10 min max min max min max t in input pad and buffer delay 0.6 1.1 1.4 ns t io i/o input pad and buffer delay 0.6 1.1 1.4 ns t fin fast input delay 2.5 3.0 3.7 ns t sexp shared expander delay 1.8 3.0 3.9 ns t pexp parallel expander delay 0.4 0.7 0.9 ns t lad logic array delay 1.5 2.5 3.2 ns t lac logic control array delay 0.6 1.0 1.2 ns t ioe internal output enable delay 0.0 0.0 0.0 ns t od1 output buffer and pad delay, slow slew rate = off v ccio = 3.3 v c1 = 35 pf 0.8 1.3 1.8 ns t od2 output buffer and pad delay, slow slew rate = off v ccio = 2.5 v c1 = 35 pf (5) 1.3 1.8 2.3 ns t od3 output buffer and pad delay, slow slew rate = on v ccio = 2.5 v or 3.3 v c1 = 35 pf 5.8 6.3 6.8 ns t zx1 output buffer enable delay, slow slew rate = off v ccio = 3.3 v c1 = 35 pf 4.0 4.0 5.0 ns t zx2 output buffer enable delay, slow slew rate = off v ccio = 2.5 v c1 = 35 pf (5) 4.5 4.5 5.5 ns t zx3 output buffer enable delay, slow slew rate = on v ccio = 3.3 v c1 = 35 pf 9.0 9.0 10.0 ns t xz output buffer disable delay c1 = 5 pf 4.0 4.0 5.0 ns t su register setup time 1.3 2.0 2.9 ns t h register hold time 0.6 1.0 1.3 ns t fsu register setup time of fast input 1.0 1.5 1.5 ns t fh register hold time of fast input 1.5 1.5 1.5 ns t rd register delay 0.7 1.2 1.6 ns t comb combinatorial delay 0.6 0.9 1.3 ns t ic array clock delay 1.2 1.9 2.5 ns altera corporation 39 max 7000a programmable logic device data sheet t en register enable time 0.6 1.0 1.2 ns t glob global control delay 1.0 1.5 2.2 ns t pre register preset time 1.3 2.1 2.9 ns t clr register clear time 1.3 2.1 2.9 ns t pia pia delay (2) 1.0 1.7 2.3 ns t lpa low-power adder (6) 3.5 4.0 5.0 ns table 20. epm7064ae internal timing parameters (part 2 of 2) note (1) symbol parameter conditions speed grade unit -4 -7 -10 min max min max min max 40 altera corporation max 7000a programmable logic device data sheet table 21. epm7128ae external timing parameters note (1) symbol parameter conditions speed grade unit -5 -7 -10 min max min max min max t pd1 input to non- registered output c1 = 35 pf (2) 5.0 7.5 10 ns t pd2 i/o input to non- registered output c1 = 35 pf (2) 5.0 7.5 10 ns t su global clock setup time (2) 3.3 4.9 6.6 ns t h global clock hold time (2) 0.0 0.0 0.0 ns t fsu global clock setup time of fast input 2.5 3.0 3.0 ns t fh global clock hold time of fast input 0.0 0.0 0.0 ns t co1 global clock to output delay c1 = 35 pf 1.0 3.4 1.0 5.0 1.0 6.6 ns t ch global clock high time 2.0 3.0 4.0 ns t cl global clock low time 2.0 3.0 4.0 ns t asu array clock setup time (2) 1.8 2.8 3.8 ns t ah array clock hold time (2) 0.2 0.3 0.4 ns t aco1 array clock to output delay c1 = 35 pf (2) 1.0 4.9 1.0 7.1 1.0 9.4 ns t ach array clock high time 2.0 3.0 4.0 ns t acl array clock low time 2.0 3.0 4.0 ns t cppw minimum pulse width for clear and preset (3) 2.0 3.0 4.0 ns t cnt minimum global clock period (2) 5.2 7.7 10.2 ns f cnt maximum internal global clock frequency (2) , (4) 192.3 129.9 98.0 mhz t acnt minimum array clock period (2) 5.2 7.7 10.2 ns f acnt maximum internal array clock frequency (2) , (4) 192.3 129.9 98.0 mhz altera corporation 41 max 7000a programmable logic device data sheet table 22. epm7128ae internal timing parameters (part 1 of 2) note (1) symbol parameter conditions speed grade unit -5 -7 -10 min max min max min max t in input pad and buffer delay 0.7 1.0 1.4 ns t io i/o input pad and buffer delay 0.7 1.0 1.4 ns t fin fast input delay 2.5 3.0 3.4 ns t sexp shared expander delay 2.0 2.9 3.8 ns t pexp parallel expander delay 0.4 0.7 0.9 ns t lad logic array delay 1.6 2.4 3.1 ns t lac logic control array delay 0.7 1.0 1.3 ns t ioe internal output enable delay 0.0 0.0 0.0 ns t od1 output buffer and pad delay, slow slew rate = off v ccio = 3.3 v c1 = 35 pf 0.8 1.2 1.6 ns t od2 output buffer and pad delay, slow slew rate = off v ccio = 2.5 v c1 = 35 pf (5) 1.3 1.7 2.1 ns t od3 output buffer and pad delay, slow slew rate = on v ccio = 2.5 v or 3.3 v c1 = 35 pf 5.8 6.2 6.6 ns t zx1 output buffer enable delay, slow slew rate = off v ccio = 3.3 v c1 = 35 pf 4.0 4.0 5.0 ns t zx2 output buffer enable delay, slow slew rate = off v ccio = 2.5 v c1 = 35 pf (5) 4.5 4.5 5.5 ns t zx3 output buffer enable delay, slow slew rate = on v ccio = 3.3 v c1 = 35 pf 9.0 9.0 10.0 ns t xz output buffer disable delay c1 = 5 pf 4.0 4.0 5.0 ns t su register setup time 1.4 2.1 2.9 ns t h register hold time 0.6 1.0 1.3 ns t fsu register setup time of fast input 1.1 1.6 1.6 ns t fh register hold time of fast input 1.4 1.4 1.4 ns t rd register delay 0.8 1.2 1.6 ns t comb combinatorial delay 0.5 0.9 1.3 ns t ic array clock delay 1.2 1.7 2.2 ns 42 altera corporation max 7000a programmable logic device data sheet t en register enable time 0.7 1.0 1.3 ns t glob global control delay 1.1 1.6 2.0 ns t pre register preset time 1.4 2.0 2.7 ns t clr register clear time 1.4 2.0 2.7 ns t pia pia delay (2) 1.4 2.0 2.6 ns t lpa low-power adder (6) 4.0 4.0 5.0 ns table 22. epm7128ae internal timing parameters (part 2 of 2) note (1) symbol parameter conditions speed grade unit -5 -7 -10 min max min max min max altera corporation 43 max 7000a programmable logic device data sheet table 23. epm7256ae external timing parameters note (1) symbol parameter conditions speed grade unit -5 -7 -10 min max min max min max t pd1 input to non- registered output c1 = 35 pf (2) 5.5 7.5 10 ns t pd2 i/o input to non- registered output c1 = 35 pf (2) 5.5 7.5 10 ns t su global clock setup time (2) 3.9 5.2 6.9 ns t h global clock hold time (2) 0.0 0.0 0.0 ns t fsu global clock setup time of fast input 2.5 3.0 3.0 ns t fh global clock hold time of fast input 0.0 0.0 0.0 ns t co1 global clock to output delay c1 = 35 pf 1.0 3.5 1.0 4.8 1.0 6.4 ns t ch global clock high time 2.0 3.0 4.0 ns t cl global clock low time 2.0 3.0 4.0 ns t asu array clock setup time (2) 2.0 2.7 3.6 ns t ah array clock hold time (2) 0.2 0.3 0.5 ns t aco1 array clock to output delay c1 = 35 pf (2) 1.0 5.4 1.0 7.3 1.0 9.7 ns t ach array clock high time 2.0 3.0 4.0 ns t acl array clock low time 2.0 3.0 4.0 ns t cppw minimum pulse width for clear and preset (3) 2.0 3.0 4.0 ns t cnt minimum global clock period (2) 5.8 7.9 10.5 ns f cnt maximum internal global clock frequency (2) , (4) 172.4 126.6 95.2 mhz t acnt minimum array clock period (2) 5.8 7.9 10.5 ns f acnt maximum internal array clock frequency (2) , (4) 172.4 126.6 95.2 mhz 44 altera corporation max 7000a programmable logic device data sheet table 24. epm7256ae internal timing parameters (part 1 of 2) note (1) symbol parameter conditions speed grade unit -5 -7 -10 min max min max min max t in input pad and buffer delay 0.7 0.9 1.2 ns t io i/o input pad and buffer delay 0.7 0.9 1.2 ns t fin fast input delay 2.4 2.9 3.4 ns t sexp shared expander delay 2.1 2.8 3.7 ns t pexp parallel expander delay 0.3 0.5 0.6 ns t lad logic array delay 1.7 2.2 2.8 ns t lac logic control array delay 0.8 1.0 1.3 ns t ioe internal output enable delay 0.0 0.0 0.0 ns t od1 output buffer and pad delay, slow slew rate = off v ccio = 3.3 v c1 = 35 pf 0.9 1.2 1.6 ns t od2 output buffer and pad delay, slow slew rate = off v ccio = 2.5 v c1 = 35 pf (5) 1.4 1.7 2.1 ns t od3 output buffer and pad delay, slow slew rate = on v ccio = 2.5 v or 3.3 v c1 = 35 pf 5.9 6.2 6.6 ns t zx1 output buffer enable delay, slow slew rate = off v ccio = 3.3 v c1 = 35 pf 4.0 4.0 5.0 ns t zx2 output buffer enable delay, slow slew rate = off v ccio = 2.5 v c1 = 35 pf (5) 4.5 4.5 5.5 ns t zx3 output buffer enable delay, slow slew rate = on v ccio = 3.3 v c1 = 35 pf 9.0 9.0 10.0 ns t xz output buffer disable delay c1 = 5 pf 4.0 4.0 5.0 ns t su register setup time 1.5 2.1 2.9 ns t h register hold time 0.7 0.9 1.2 ns t fsu register setup time of fast input 1.1 1.6 1.6 ns t fh register hold time of fast input 1.4 1.4 1.4 ns t rd register delay 0.9 1.2 1.6 ns t comb combinatorial delay 0.5 0.8 1.2 ns altera corporation 45 max 7000a programmable logic device data sheet t ic array clock delay 1.2 1.6 2.1 ns t en register enable time 0.8 1.0 1.3 ns t glob global control delay 1.0 1.5 2.0 ns t pre register preset time 1.6 2.3 3.0 ns t clr register clear time 1.6 2.3 3.0 ns t pia pia delay (2) 1.7 2.4 3.2 ns t lpa low-power adder (6) 4.0 4.0 5.0 ns table 24. epm7256ae internal timing parameters (part 2 of 2) note (1) symbol parameter conditions speed grade unit -5 -7 -10 min max min max min max 46 altera corporation max 7000a programmable logic device data sheet table 25. epm7512ae external timing parameters note (1) symbol parameter conditions speed grade unit -7 -10 -12 min max min max min max t pd1 input to non- registered output c1 = 35 pf (2) 7.5 10.0 12.0 ns t pd2 i/o input to non- registered output c1 = 35 pf (2) 7.5 10.0 12.0 ns t su global clock setup time (2) 5.6 7.6 9.1 ns t h global clock hold time (2) 0.0 0.0 0.0 ns t fsu global clock setup time of fast input 3.0 3.0 3.0 ns t fh global clock hold time of fast input 0.0 0.0 0.0 ns t co1 global clock to output delay c1 = 35 pf 1.0 4.7 1.0 6.3 1.0 7.5 ns t ch global clock high time 3.0 4.0 5.0 ns t cl global clock low time 3.0 4.0 5.0 ns t asu array clock setup time (2) 2.5 3.5 4.1 ns t ah array clock hold time (2) 0.2 0.3 0.4 ns t aco1 array clock to output delay c1 = 35 pf (2) 1.0 7.8 1.0 10.4 1.0 12.5 ns t ach array clock high time 3.0 4.0 5.0 ns t acl array clock low time 3.0 4.0 5.0 ns t cppw minimum pulse width for clear and preset (3) 3.0 4.0 5.0 ns t cnt minimum global clock period (2) 8.6 11.5 13.9 ns f cnt maximum internal global clock frequency (2) , (4) 116.3 87.0 71.9 mhz t acnt minimum array clock period (2) 8.6 11.5 13.9 ns f acnt maximum internal array clock frequency (2) , (4) 116.3 87.0 71.9 mhz altera corporation 47 max 7000a programmable logic device data sheet table 26. epm7512ae internal timing parameters (part 1 of 2) note (1) symbol parameter conditions speed grade unit -7 -10 -12 min max min max min max t in input pad and buffer delay 0.7 0.9 1.0 ns t io i/o input pad and buffer delay 0.7 0.9 1.0 ns t fin fast input delay 3.1 3.6 4.1 ns t sexp shared expander delay 2.7 3.5 4.4 ns t pexp parallel expander delay 0.4 0.5 0.6 ns t lad logic array delay 2.2 2.8 3.5 ns t lac logic control array delay 1.0 1.3 1.7 ns t ioe internal output enable delay 0.0 0.0 0.0 ns t od1 output buffer and pad delay, slow slew rate = off v ccio = 3.3 v c1 = 35 pf 1.0 1.5 1.7 ns t od2 output buffer and pad delay, slow slew rate = off v ccio = 2.5 v c1 = 35 pf (5) 1.5 2.0 2.2 ns t od3 output buffer and pad delay, slow slew rate = on v ccio = 2.5 v or 3.3 v c1 = 35 pf 6.0 6.5 6.7 ns t zx1 output buffer enable delay, slow slew rate = off v ccio = 3.3 v c1 = 35 pf 4.0 5.0 5.0 ns t zx2 output buffer enable delay, slow slew rate = off v ccio = 2.5 v c1 = 35 pf (5) 4.5 5.5 5.5 ns t zx3 output buffer enable delay, slow slew rate = on v ccio = 3.3 v c1 = 35 pf 9.0 10.0 10.0 ns t xz output buffer disable delay c1 = 5 pf 4.0 5.0 5.0 ns t su register setup time 2.1 3.0 3.5 ns t h register hold time 0.6 0.8 1.0 ns t fsu register setup time of fast input 1.6 1.6 1.6 ns t fh register hold time of fast input 1.4 1.4 1.4 ns t rd register delay 1.3 1.7 2.1 ns t comb combinatorial delay 0.6 0.8 1.0 ns 48 altera corporation max 7000a programmable logic device data sheet t ic array clock delay 1.8 2.3 2.9 ns t en register enable time 1.0 1.3 1.7 ns t glob global control delay 1.7 2.2 2.7 ns t pre register preset time 1.0 1.4 1.7 ns t clr register clear time 1.0 1.4 1.7 ns t pia pia delay (2) 3.0 4.0 4.8 ns t lpa low-power adder (6) 4.5 5.0 5.0 ns table 26. epm7512ae internal timing parameters (part 2 of 2) note (1) symbol parameter conditions speed grade unit -7 -10 -12 min max min max min max altera corporation 49 max 7000a programmable logic device data sheet table 27. epm7128a external timing parameters note (1) symbol parameter conditions speed grade unit -6 -7 -10 -12 minmaxminmaxminmaxminmax t pd1 input to non-registered output c1 = 35 pf (2) 6.0 7.5 10.0 12.0 ns t pd2 i/o input to non- registered output c1 = 35 pf (2) 6.0 7.5 10.0 12.0 ns t su global clock setup time (2) 4.2 5.3 7.0 8.5 ns t h global clock hold time (2) 0.0 0.0 0.0 0.0 ns t fsu global clock setup time of fast input 2.5 3.0 3.0 3.0 ns t fh global clock hold time of fast input 0.0 0.0 0.0 0.0 ns t co1 global clock to output delay c1 = 35 pf 1.0 3.7 1.0 4.6 1.0 6.1 1.0 7.3 ns t ch global clock high time 3.0 3.0 4.0 5.0 ns t cl global clock low time 3.0 3.0 4.0 5.0 ns t asu array clock setup time (2) 1.9 2.4 3.1 3.8 ns t ah array clock hold time (2) 1.5 2.2 3.3 4.3 ns t aco1 array clock to output delay c1 = 35 pf (2) 1.0 6.0 1.0 7.5 1.0 10.0 1.0 12.0 ns t ach array clock high time 3.0 3.0 4.0 5.0 ns t acl array clock low time 3.0 3.0 4.0 5.0 ns t cppw minimum pulse width for clear and preset (3) 3.0 3.0 4.0 5.0 ns t cnt minimum global clock period (2) 6.9 8.6 11.5 13.8 ns f cnt maximum internal global clock frequency (2) , (4) 144.9 116.3 87.0 72.5 mhz t acnt minimum array clock period (2) 6.9 8.6 11.5 13.8 ns f acnt maximum internal array clock frequency (2) , (4) 144.9 116.3 87 72.5 mhz 50 altera corporation max 7000a programmable logic device data sheet table 28. epm7128a internal timing parameters (part 1 of 2) note (1) symbol parameter conditions speed grade unit -6 -7 -10 -12 min max min max min max min max t in input pad and buffer delay 0.6 0.7 0.9 1.1 ns t io i/o input pad and buffer delay 0.6 0.7 0.9 1.1 ns t fin fast input delay 2.7 3.1 3.6 3.9 ns t sexp shared expander delay 2.5 3.2 4.3 5.1 ns t pexp parallel expander delay 0.7 0.8 1.1 1.3 ns t lad logic array delay 2.4 3.0 4.1 4.9 ns t lac logic control array delay 2.4 3.0 4.1 4.9 ns t ioe internal output enable delay 0.0 0.0 0.0 0.0 ns t od1 output buffer and pad delay, slow slew rate = off v ccio = 3.3 v c1 = 35 pf 0.4 0.6 0.7 0.9 ns t od2 output buffer and pad delay, slow slew rate = off v ccio = 2.5 v c1 = 35 pf (5) 0.9 1.1 1.2 1.4 ns t od3 output buffer and pad delay, slow slew rate = on v ccio = 2.5 v or 3.3 v c1 = 35 pf 5.4 5.6 5.7 5.9 ns t zx1 output buffer enable delay, slow slew rate = off v ccio = 3.3 v c1 = 35 pf 4.0 4.0 5.0 5.0 ns t zx2 output buffer enable delay, slow slew rate = off v ccio = 2.5 v c1 = 35 pf (5) 4.5 4.5 5.5 5.5 ns t zx3 output buffer enable delay, slow slew rate = on v ccio = 3.3 v c1 = 35 pf 9.0 9.0 10.0 10.0 ns t xz output buffer disable delay c1 = 5 pf 4.0 4.0 5.0 5.0 ns t su register setup time 1.9 2.4 3.1 3.8 ns t h register hold time 1.5 2.2 3.3 4.3 ns t fsu register setup time of fast input 0.8 1.1 1.1 1.1 ns t fh register hold time of fast input 1.7 1.9 1.9 1.9 ns altera corporation 51 max 7000a programmable logic device data sheet t rd register delay 1.7 2.1 2.8 3.3 ns t comb combinatorial delay 1.7 2.1 2.8 3.3 ns t ic array clock delay 2.4 3.0 4.1 4.9 ns t en register enable time 2.4 3.0 4.1 4.9 ns t glob global control delay 1.0 1.2 1.7 2.0 ns t pre register preset time 3.1 3.9 5.2 6.2 ns t clr register clear time 3.1 3.9 5.2 6.2 ns t pia pia delay (2) 0.9 1.1 1.5 1.8 ns t lpa low-power adder (6) 11.0 10.0 10.0 10.0 ns table 28. epm7128a inter nal timing parameters (part 2 of 2) note (1) symbol parameter conditions speed grade unit -6 -7 -10 -12 min max min max min max min max 52 altera corporation max 7000a programmable logic device data sheet table 29. epm7256a external timing parameters note (1) symbol parameter conditions speed grade unit -6 -7 -10 -12 min max min max min max min max t pd1 input to non-registered output c1 = 35 pf (2) 6.0 7.5 10.0 12.0 ns t pd2 i/o input to non- registered output c1 = 35 pf (2) 6.0 7.5 10.0 12.0 ns t su global clock setup time (2) 3.7 4.6 6.2 7.4 ns t h global clock hold time (2) 0.0 0.0 0.0 0.0 ns t fsu global clock setup time of fast input 2.5 3.0 3.0 3.0 ns t fh global clock hold time of fast input 0.0 0.0 0.0 0.0 ns t co1 global clock to output delay c1 = 35 pf 1.0 3.3 1.0 4.2 1.0 5.5 1.0 6.6 ns t ch global clock high time 3.0 3.0 4.0 4.0 ns t cl global clock low time 3.0 3.0 4.0 4.0 ns t asu array clock setup time (2) 0.8 1.0 1.4 1.6 ns t ah array clock hold time (2) 1.9 2.7 4.0 5.1 ns t aco1 array clock to output delay c1 = 35 pf (2) 1.0 6.2 1.0 7.8 1.0 10.3 1.0 12.4 ns t ach array clock high time 3.0 3.0 4.0 4.0 ns t acl array clock low time 3.0 3.0 4.0 4.0 ns t cppw minimum pulse width for clear and preset (3) 3.0 3.0 4.0 4.0 ns t cnt minimum global clock period (2) 6.4 8.0 10.7 12.8 ns f cnt maximum internal global clock frequency (2) , (4) 156.3 125.0 93.5 78.1 mhz t acnt minimum array clock period (2) 6.4 8.0 10.7 12.8 ns f acnt maximum internal array clock frequency (2) , (4) 156.3 125.0 93.5 78.1 mhz altera corporation 53 max 7000a programmable logic device data sheet table 30. epm7256a internal timing parameters (part 1 of 2) note (1) symbol parameter conditions speed grade unit -6 -7 -10 -12 min max min max min max min max t in input pad and buffer delay 0.3 0.4 0.5 0.6 ns t io i/o input pad and buffer delay 0.3 0.4 0.5 0.6 ns t fin fast input delay 2.4 3.0 3.4 3.8 ns t sexp shared expander delay 2.8 3.5 4.7 5.6 ns t pexp parallel expander delay 0.5 0.6 0.8 1.0 ns t lad logic array delay 2.5 3.1 4.2 5.0 ns t lac logic control array delay 2.5 3.1 4.2 5.0 ns t ioe internal output enable delay 0.2 0.3 0.4 0.5 ns t od1 output buffer and pad delay, slow slew rate = off v ccio = 3.3 v c1 = 35 pf 0.3 0.4 0.5 0.6 ns t od2 output buffer and pad delay, slow slew rate = off v ccio = 2.5 v c1 = 35 pf (5) 0.8 0.9 1.0 1.1 ns t od3 output buffer and pad delay slow slew rate = on v ccio = 2.5 v or 3.3 v c1 = 35 pf 5.3 5.4 5.5 5.6 ns t zx1 output buffer enable delay slow slew rate = off v ccio = 3.3 v c1 = 35 pf 4.0 4.0 5.0 5.0 ns t zx2 output buffer enable delay slow slew rate = off v ccio = 2.5 v c1 = 35 pf (5) 4.5 4.5 5.5 5.5 ns t zx3 output buffer enable delay slow slew rate = on v ccio = 2.5 v or 3.3 v c1 = 35 pf 9.0 9.0 10.0 10.0 ns t xz output buffer disable delay c1 = 5 pf 4.0 4.0 5.0 5.0 ns t su register setup time 1.0 1.3 1.7 2.0 ns t h register hold time 1.7 2.4 3.7 4.7 ns t fsu register setup time of fast input 1.2 1.4 1.4 1.4 ns t fh register hold time of fast input 1.3 1.6 1.6 1.6 ns t rd register delay 1.6 2.0 2.7 3.2 ns 54 altera corporation max 7000a programmable logic device data sheet notes to tables: (1) these values are specified under the re commended operating co nditions shown in table 14 on page 28 . see figure 12 for more information on switching waveforms. (2) these values are specified for a pia fan-out of one lab (16 macrocells). for each additional lab fan-out in these devices, add an additional 0.1 ns to the pia timing value. (3) this minimum pulse width for preset and clear app lies for both global clear and array controls. the t lpa parameter must be added to this minimum width if the clear or reset sign al incorporates the t lad parameter into the signal path. (4) this parameter is measured with a 16-bit loadable , enabled, up/down counter programmed into each lab. (5) operating conditions: v ccio = 2.5 0.2 v for commercial and industrial use. (6) the t lpa parameter must be added to the t lad , t lac , t ic , t en , t sexp , t acl , and t cppw parameters for macrocells running in low-power mode. power consumption supply power (p) versus frequency ( f max , in mhz) for max 7000a devices is calculated with the following equation: p = p int + p io = i ccint v cc + p io the p io value, which depends on the devi ce output load characteristics and switching frequency, can be calculated using the guidelines given in application note 74 (evaluatin g power for altera devices) . the i ccint value depends on the switching frequency and the application logic. the i ccint value is calculated with the following equation: i ccint = (a mc ton ) + [b (mc dev ? mc ton )] + (c mc used f max tog lc ) t comb combinatorial delay 1.6 2.0 2.7 3.2 ns t ic array clock delay 2.7 3.4 4.5 5.4 ns t en register enable time 2.5 3.1 4.2 5.0 ns t glob global control delay 1.1 1.4 1.8 2.2 ns t pre register preset time 2.3 2.9 3.8 4.6 ns t clr register clear time 2.3 2.9 3.8 4.6 ns t pia pia delay (2) 1.3 1.6 2.1 2.6 ns t lpa low-power adder (6) 11.0 10.0 10.0 10.0 ns table 30. epm7256a internal timing parameters (part 2 of 2) note (1) symbol parameter conditions speed grade unit -6 -7 -10 -12 min max min max min max min max altera corporation 55 max 7000a programmable logic device data sheet the parameters in this equation are: mc ton = number of macrocells with the turbo bit option turned on, as reported in the max+plus ii report file ( .rpt ) mc dev = number of macrocells in the device mc used = total number of macrocells in the design, as reported in the report file f max = highest clock frequency to the device tog lc = average percentage of logic cells toggling at each clock (typically 12.5 % ) a, b, c = constants, shown in table 31 this calculation provides an i cc estimate based on typical conditions using a pattern of a 16-bit, loadable , enabled, up/down counter in each lab with no output load. actual i cc should be verified during operation because this measurement is sensitive to the actual pattern in the device and the environmental operating conditions. table 31. max 7000a i cc equation constants device a b c epm7032ae 0.71 0.30 0.014 epm7064ae 0.71 0.30 0.014 epm7128a 0.71 0.30 0.014 epm7128ae 0.71 0.30 0.014 epm7256a 0.71 0.30 0.014 epm7256ae 0.71 0.30 0.014 epm7512ae 0.71 0.30 0.014 56 altera corporation max 7000a programmable logic device data sheet figure 13 shows the typical supply current versus frequency for max 7000a devices. figure 13. i cc vs. frequency for max 7000a devices (part 1 of 2) v cc = 3.3 v room temperature 0 frequency (mhz) high speed low power 50 100 1 5 0 200 192.3 mhz 108.7 mhz 250 epm7128a & epm7128ae epm7032ae v cc = 3.3 v room temperature frequency (mhz) 30 40 60 70 80 v cc = 3.3 v room temperature 0 frequency (mhz) high speed low power 50 100 1 5 0 200 222.2 mhz 125.0 mhz 250 0 50 100 1 5 0 200 250 epm7064ae 10 50 20 10 15 25 30 35 40 high speed low power 227.3 mhz 144.9 mhz 20 5 typical i active (ma) cc typical i active (ma) cc typical i active (ma) cc 60 80 120 140 160 20 100 40 altera corporation 57 max 7000a programmable logic device data sheet figure 13. i cc vs. frequency for max 7000a devices (part 2 of 2) device pin-outs see the altera web site ( http://www.altera.com ) or the altera digital library for pin-out information. figures 14 through 23 show the package pin-out diagrams for max 7000a devices. figure 14. 44-pin plcc/tqfp package pin-out diagram package outlines no t drawn to scale. epm7256a & epm7256ae v cc = 3.3 v room temperature frequency (mhz) low power 172.4 mhz 102.0 mhz 50 100 150 200 250 300 high speed 0 50 100 1 5 0 200 typical i active (ma) cc epm7512ae v cc = 3.3 v room temperature frequency (mhz) low power 116.3 mhz 76.3 mhz 100 200 300 400 500 600 0 20 40 80 100 typical i active (ma) cc high speed 60 120 140 44-pin plcc i/o i/o i/o vcc input/oe2/gclk2 input/gclrn input/oe1n input/gclk1 gnd i/o i/o i/o i/o/tdo i/o i/o vcc i/o i/o i/o/tck i/o gnd i/o i/o i/o i/o i/o gnd vcc i/o i/o i/o i/o i/o 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 epm7032ae epm7064ae i/o/tdi i/o i/o gnd i/o i/o i/o/tms i/o vcc i/o i/o 44-pin tqfp pin 12 pin 23 pin 34 pin 1 i/o i/o i/o vcc input/oe2/gclk2 input/gclrn input/oe1n input/gclk1 gnd i/o i/o i/o i/o/tdo i/o i/o vcc i/o i/o i/o/tck i/o gnd i/o i/o i/o i/o i/o gnd vcc i/o i/o i/o i/o i/o i/o/tdi i/o i/o gnd i/o i/o i/o/tms i/o vcc i/o i/o epm7032ae epm7064ae 58 altera corporation max 7000a programmable logic device data sheet figure 15. 49-pin ultra fineline bga package pin-out diagram package outlines not drawn to scale. figure 16. 84-pin plcc package pin-out diagram package outline no t drawn to scale. indicates location of ball a1 a1 ball pad corner a b c d e f g 7654321 epm7064ae i/o vccio i/o/tdi i/o i/o i/o i/o gnd i/o i/o i/o i/o/tms i/o vccio i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o gnd i/o i/o i/o vccint input/oe2/gclk2 input/glcrn input/oe1 input/gclk1 gnd i/o i/o i/o vccio i/o i/o i/o 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 i/o i/o gnd i/o/tdo i/o i/o i/o i/o vccio i/o i/o i/o i/o/tck i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o vccio i/o i/o i/o gnd vccint i/o i/o i/o gnd i/o i/o i/o i/o i/o vccio 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 epm7128a epm7128ae i/o altera corporation 59 max 7000a programmable logic device data sheet figure 17. 100-pin tqfp package pin-out diagram package outline not drawn to scale. figure 18. 100-pin fineline bga package pin-out diagram pin 1 pin 26 pin 76 pin 51 epm7064ae epm7128a epm7128ae epm7256a epm7256ae indicates location of ball a1 a1 ball pad corner a b c d e f g h j k 10987 6543 2 1 epm7064ae epm7128a epm7128ae epm7256ae package outline no t drawn to scale. 60 altera corporation max 7000a programmable logic device data sheet figure 19. 144-pin tqfp package pin-out diagram package outline no t drawn to scale . figure 20. 169-pin ultra fineli ne bga package pin-out diagram package outline no t drawn to scale . indicates location of pin 1 pin 1 pin 109 pin 73 pin 37 epm7128a epm7128ae epm7256a epm7256ae epm7512ae indicates location of ball a1 a1 ball pad corner a b c d e f g h j k 10 9 8 7 6 5 4 3 2 1 epm7064ae epm7128a epm7128ae epm7256ae altera corporation 61 max 7000a programmable logic device data sheet figure 21. 208-pin pqfp package pin-out diagram package outline not drawn to scale . pin 1 pin 157 pin 105 pin 53 epm7256a epm7256ae epm7512ae 62 altera corporation max 7000a programmable logic device data sheet figure 22. 256-pin bga package pin-out diagram package outline no t drawn to scale. indicates location of ball a1 a1 ball pad corner g f e d c b a h j k l m n p r t 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 epm7512ae u v w y 17 18 19 20 altera corporation 63 max 7000a programmable logic device data sheet figure 23. 256-pin fineline bga package pin-out diagram package outline not drawn to scale . revision history the information contained in the max 7000a programmable logic device data sheet version 4.5 supersedes information published in previous versions. version 4.5 the following changes were made in the max 7000a progra mmable logic device data sheet version 4.5: updated text in the ?power sequencing & hot-socketing? section. version 4.4 the following changes were made in the max 7000a progra mmable logic device data sheet version 4.4: added tables 5 through 7 . added ?programming sequence? on page 17 and ?programming times? on page 18 . indicates location of ball a1 a1 ball pad corner g f e d c b a h j k l m n p r t 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 epm7128a epm7128ae epm7256a epm7256ae epm7512ae copyright ? 2003 altera corporation. all rights reserv ed. altera, the programmable solutions company, the stylized altera logo, specific device designations , and all other words and lo gos that are identified as trademarks and/or se rvice marks are, unless noted otherwise, the trademarks and service marks of altera corporation in the u.s. and other countries. all other product or service names are the property of their respective holders. altera produc ts are protected under numerous u. s. and foreign patents and pending applications, maskwork rights, and copyrights. altera warrants performance of its semiconductor products to current specifications in accord ance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability arising out of the appli cation or use of any information, product, or service described herein except as expressly agreed to in writing by altera corporation. altera customers are advised to obtain the la test version of device specifications before relying on any published information and befo re placing orders for products or services . 101 innovation drive san jose, ca 95134 (408) 544-7000 http://www.altera.com applications hotline: (800) 800-epld literature services: lit_req@altera.com max 7000a programmable logic device data sheet 64 altera corporation version 4.3 the following changes were made in the max 7000a programmable logic device data sheet version 4.3: added extended temperature devices to document updated table 14 . version 4.2 the following changes were made in the max 7000a programmable logic device data sheet version 4.2: removed note (1) from table 2 . removed note (4) from tables 3 and 4 . version 4.1 the following changes were made in the max 7000a programmable logic device data sheet version 4.1: updated leakage current information in table 15 . updated note (9) of table 15 . updated note (1) of tables 17 through 30 . |
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